The present invention relates to digital imaging circuits and more specifically to efficient processing in such circuits in test and/or normal mode operation.
Various types of digital imaging circuits are known in the art and they include circuits based on charge coupled devices (CCD) and active pixel sensors (APS). One difference between CCDs and APSs is that APSs include an active device such as a transistor in each pixel cell and hence their name stems from the presence of these active devices. A typical APS cell includes a photo diode and several transistors and has a reset, row and column node (see FIG. 2). While the present invention is particularly applicable to APSs, the delayed continuous signal propagation and other aspects of the present invention are applicable to other digital imaging circuits and to memory cell arrays.
APSs are typically fabricated in a semiconductive media. Each APS in a wafer must be tested for proper operation and a certain rejection ratio is expected. Many problems that cause rejection or failure are related to the integrity of the metal conductive material. Integrity issues normally arise from three areas: (1) voids in the conductive material that cause open circuits; (2) extraneous conductive material that causes shorts; and (3) corruption of vertical layers, for example, due to pinholes in insulating layers, etc.
Various metal integrity tests are currently carried out on conductors within APSs. These tests typically include individually and sequentially selecting each row in an array and then repeating this process for the reset and column conductors. This testing arrangement requires a significant amount of time to process all testing signals and necessitates a significant amount of logic to process the signals. It should be recognized that in APS circuits approximately ⅔-xc2xe of a die typically comprises the APS, leaving little room for decode, test and other processing circuitry. Furthermore, some conventional testing is done with analog signals that require additional analog to digital converters and programmable gain amplifiers for signal processing.
With respect to normal mode operation, the present invention provides faster signal processing than in prior art APSs, particularly with respect to the reset signal. When taking a xe2x80x9cpicture,xe2x80x9d it is necessary that the reset signal for all cells be asserted at approximately the same time (to reduce gradient across an image) and it is necessary that this signal assertion not create an unacceptable current spike. One prior art embodiment sequentially enables or disables each row of cells. Since each row takes at least three clock cycles, this requires 120 ns per row which (at 25 mHz) is 154 us for a pixel array of 1280 rows. This does not meet camera vendor specifications of 50 us or less. Another prior art embodiment sends out a global reset (or enable/disable) signal. While this satisfies the timing requirement, parasitic capacitance creates a 5 mA current spike per row resulting in a 6.4 A current spike for the array, which is unacceptable.
Thus, a need exists for asserting the reset signal for an array of pixel cells in a rapid manner that does not introduce undesired EMI.
Accordingly, it is an object of the present invention to provide an imaging circuit with an APS that provides efficient testing.
It is another object of the present invention to provide an imaging circuit with an APS that efficiently tests the integrity of row, reset and column conductors.
It is also an object of the present invention to provide an imaging circuit with an APS that provide rapid enabling/disabling of cells therein in a manner that does not generate undesirable EMI levels.
These and related objects of the present invention are achieved by use of an improved digital imaging circuit and method as described herein.
The present invention may be practiced in many embodiments. The present invention, in at least one embodiment, includes a plurality of selectably enableable coupling conductors that are provided between each of a particular type of principal conductors, such as the row, reset or column type of conductor. The coupling conductors can be enabled such that a signal propagated on to one conductor is propagated on to other like (or potentially unlike) conductors. In test mode, this arrangement may, for example, detect metal integrity faults. In operation mode, this arrangement may, for example, provide a global signal in a manner that is rapid, but does not cause an undesirable current (EMI) spike. The coupling conductors are preferably provided near or at the ends of conductors to in effectively create a continuous and temporary generally serial signal conductor that tends to be formed in a serpentine manner through an active pixel sensor array. This selectable coupling arrangement may be provided for all, some or one of the principal conductor types.